1. Field of the Invention
The present invention relates to output drivers for integrated circuits; and specifically to driving capacitive output loads external to the chip with digital levels while minimizing noise generated by parasitic bond wire lead inductance.
2. Discussion of the Related Art
Noise generated by digital switching has been identified as a significant obstacle to the acceptance of new, high speed digital devices. As switching speeds and dynamic drive capability are increased, voltage perturbations on expected-quiet outputs increase as well.
Integrated circuits typically must drive output pads which are bonded to package leads through bonding wires. Because the capacitances of circuit nodes on a circuit board are very large in comparison with most node capacitances internal to the integrated circuit, signals which are to be communicated outside the integrated circuit must be amplified by large output buffers which then drive the output pads and the potentially large capacitive loads to which the output pads are connected. Unfortunately, the bonding wires have non-zero inductances which can generate noise both inside and outside the integrated circuits to which they connect. In many integrated circuits, the current driving capabilities of the output buffers is larger than the total current driving capabilities of all the internal devices on the integrated circuit. Thus, the output buffers often constitute a large portion of the total current used by a given integrated circuit. Moreover, in synchronous circuits, often many of the output buffers switch states (from low to high or from high to low) simultaneously directly after a clock edge. Because the output buffers are large and potentially many of them are switching simultaneously, the current consumption of the integrated circuit as a whole can contain "spikes" as the output buffers change states. During these spikes, large currents flow through the bonding wires which connect to the power and ground pads. Because these power and ground bonding leads have non-zero inductances, the large changes in currents through them induce voltages across the bonding leads. Therefore, the entire power and ground supplies for the integrated circuit can "bounce" up and down.
In digital circuits, which are inherently designed to operate under circumstances of some noise, if the bounce is severe enough, noise margins are sacrificed and errors occur. In analog portions of the circuit, power and ground bouncing usually has greater impact than in digital circuits, directly affecting the accuracy of the circuits. For example, in analog circuits, the ground bounce itself is a major problem as it can modify the reference voltage levels of sensitive inputs.
Thus, high speed digital output buffers inherently produce high amounts of noise due to the bonding wire inductances. Even if the power and ground is not supplied through bonding wires, the noise produced by each output buffer is then capacitively coupled to the other sections of the circuit.
The charging and discharging of the load capacitances require current pulses. Changes in the power supply or ground line currents generate voltage pulses across the series inductor. A fundamental limit for this rail bounce can be understood from FIGS. 1A, 1B, and 1C. If the output must be charged from the ground potential to +Vdd in a total period of time T, the optimal approach to accomplish this result is to gradually increase the output current from time zero to time T/2 and then decrease it back to zero from time T/2 to time T, as illustrated in current trace 101 FIG. 1A. The output voltage is given by the following equation. ##EQU1##
In the above equation, C is the total output node capacitance, the maximum current Imax must satisfy the following relation so that the area underneath the current curve 101 illustrated in FIG. 1A equals is exactly enough charge to change the voltage of the capacitance C from zero to +Vdd, as illustrated by the voltage trace 102 in FIG. 1B. ##EQU2##
However, changes in the output buffer load current will generate an induced voltage across the series bonding wire lead inductance according to the following equation. ##EQU3##
In the ideal case, the maximum ground bounce voltage is given by the following equation, and is illustrated by the vertical voltage drop occurring at time T/2 in FIG. 1C as the induced voltage changes from the trace 103 to the trace 104. ##EQU4##
In real non-ideal circuits, the lead inductances act as reactive elements in an under-damped oscillating system, such that damped ringing occurs. Therefore, in realistic circuits, the peak bounce voltage is significantly higher than that given by equation (4) and illustrated in FIG. 1C.
Moreover, at high speed it is extremely difficult to generate an output current which behaves as a linear ramp as illustrated in FIG. 1A. Most designs are constrained by a maximum propagation delay in the output buffers. Most applications provide a minimum operating frequency, which provides the constraint on the maximum delay time T. This should be guaranteed under all process-voltage-temperature (PVT) conditions. The PVT "corners" represent the worst extreme cases under which the circuit may be called upon to operate. For example, in a CMOS design, slow p-type diffusion and slow n-type diffusion represent one process corner. Under all load conditions and all PVT corners and extremes, full output load charging and discharging within the maximum delay time T must be guaranteed.
However, in order to minimize the inductive noise generated, a constant delay time is preferable to a minimal delay time even though the output buffer is capable of charging faster necessary to meet the maximum delay time T. FIG. 1B illustrates that the optimal output buffer produces the same output load voltage 102 over time regardless of the size of the output load. The dotted current trace 105 in FIG. 1A illustrates the optimal output buffer current under lighter output load conditions. The dotted ground bounce voltage traces 106 and 107 In FIG. 1C illustrate that the induced ground bounce is lower under lighter load capacitance conditions. Thus, if the rate of charging and discharging could be made proportional to the output load capacitance, minimal noise would be induced. A first order analysis indicates that a constant propagation delay is desirable, since lower bounce voltages are obtainable under light capacitive load conditions.
High speed mixed-mode circuit designs include analog and digital circuitry. In such mixed-mode circuits, the importance in maintaining low noise conditions for the analog circuit sections necessitates careful design of the noise-inducing digital parts of the circuit. The ground and supply line bounce inherently generated in the digital output buffers by the presence of the parasitic bonding wire inductance not only can modify the reference levels of sensitive analog inputs, but can also couple capacitively or through the common substrate into the analog sections of the circuit.
Previous output buffers designs have attempted to reduce the digital switching noise by controlling the current in the output devices. This technique has certain limitations, since the maximum current (and thus the ground/power bounce) is undesirably strongly dependent on temperature, process, or power supply variations. Moreover, given a fixed shape of the output current, the propagation delay of the output buffer is dependent on the capacitive load.
As is apparent from the above discussion, a need exists for a constant propagation delay, low-noise digital output buffer for CMOS integrated circuits.